1. Field of the Invention
The present invention relates to a semiconductor apparatus and a semiconductor memory apparatus. More particularly, the present invention relates to a semiconductor apparatus and a semiconductor memory apparatus which can easily attain a reduction of an access time.
2. Description of the Related Art
A conventional technique is described with reference to FIG. 1. FIG. 1 shows a schematic configuration of a circuit on a memory chip 10. The circuit of the memory chip 10 is an asynchronous type in which various signals are randomly inputted without a synchronization with a clock signal. A RAM core 12 in which memory cells are provided is mounted on the memory chip 10.
A plurality of control signals CE2, /CE1 (a bar of CE1), /LB (a bar of LB), /UB (a bar of UB), A1 and A0 which are used for selecting the memory cells are inputted from a plurality of pins (pads) Pd mounted on an outer circumference of the memory chip 10, respectively. Here, the control signal CE is a chip-enable signal to select the memory chip 10. The control signals A1, A0 are address signals to select bit lines of the memory cells in the RAM 12.
The memory cell is selected if all the plurality of control signals CE2, /CE1, /LB, /UB, A1 and A0 are at a selected state. If the memory cell is at a non-selected state, the memory chip 10 is designed such that a current does not flow through the memory chip 10, in order to reduce a consumptive electric power. Here, an order of a power cut logic at a first stage of input is the CE2 signal greater than the /CE1 signal greater than the /LB signal, the /UB signal greater than other input signals. That is, if the CE2 signal is at the non-selected state, a current does not flow through all paths in the memory chip 10 immediately at that time (whether or not other control signals including the /CE1 signal is at the selected state or at the non-selected state).
In a case of the configuration in FIG. 1, a read-out access worst path in which the access time for reading out the memory cell is the slowest is as follows.
CE2 Signalxe2x88x92Path (A)xe2x86x92Logic with /CE1 (OR Circuit 14)xe2x88x92Path (B)xe2x86x92Logic with /LB, /UB (OR Circuit 16)xe2x88x92Path (C)xe2x86x92Chip Underside Input Buffer 13.
Typically, in the memory chip 10, the Pads Pd are arranged on a top side and a bottom side of the memory chip 10, and the memory chip 10 is the chip longer in a longitudinal direction. Thus, this arrangement results in a problem of a signal transmission delay caused by long wirings (the paths (A), (B) and (C) between the top and bottom sides.
As mentioned above, since the delay amount (access time) of the CE2 signal becomes maximum, a speed derivation is limited. As a result of a simulation in 8 megabyte low power static random access memory (8MLPSRAM), although an access time of an Add (address) signal (the A0, A1 signals in FIG. 1) is 50 ns, an access time of the CE2 signal is 57 ns. Thus, this leads to an increase of 14%.
A long side 15 of the memory chip 10 is about 8 to 12 mm. As shown in FIG. 1, the CE2 signal passes through the long side 15 of the memory chip 10 three times, in the paths (A), (B) and (C). Correspondingly to it, the delay amount is larger, which causes an access performance of the signal in the CE system to be deteriorated.
By the way , the above-mentioned problems are common to memory apparatuses such as SRAM, a flash memory and the like. A semiconductor memory apparatus is desirable in which the access time is short.
Japanese Laid Open Patent Application (JP-A-Heisei, 8-102492) discloses a programmable wiring circuit as described below. This is provided with: input output terminals regularly arranged on a chip; input output lines respectively mounted in those input output terminals for sending and receiving a data between a wiring route within the chip and the input output terminals; a general wiring formed on the semiconductor chip so as to form any wiring route; a bypass wiring for bypassing the general wiring for each predetermined length; and wiring connection points composed of program elements arranged in a form of array at respective intersections of the input output lines, the general wiring and the bypass wiring for changing the connection conditions between each other to thereby control the wiring route.
The present invention is accomplished in view of the above mentioned problems. Therefore, an object of the present invention is to provide a semiconductor apparatus and a semiconductor memory apparatus which can easily attain a reduction of an access time.
In order to achieve an aspect of the present invention, a semiconductor apparatus, includes: an input unit inputting a first signal and a generation signal, the generation signal being generated based on the first signal and a second signal; and a control unit controlling the input unit such that one of the first signal and the generation signal is outputted, and wherein the input unit inputs the first signal prior to the generation signal, and wherein the control unit controls the input unit such that the generation signal instead of the first signal is outputted after an expiration of a predetermined time.
In this case, the control unit controls the input unit such that the first signal is outputted from the input unit until the generation signal is inputted to the input unit after the first signal is inputted to the input unit, and the generation signal instead of the first signal is outputted from the input unit when the generation signal is inputted to the input unit.
In order to achieve another aspect of the present invention, a semiconductor apparatus, includes: a delay unit outputting a first delay signal obtained by delaying a first signal by a predetermined delay amount; a control signal generating unit generating a control signal based on the first signal and the first delay signal; and a signal outputting unit inputting the first signal and a generation signal to output one of the first signal and the generation signal in response to the control signal, the generation signal being generated based on the first signal and a second signal.
In this case, the predetermined delay amount is a substantially identical with a time that elapsed before the generation signal is inputted to the signal outputting unit after the first signal is inputted to the signal outputting unit.
Also in this case, the predetermined delay amount is longer than a time that elapsed before the generation signal is inputted to the signal outputting unit after the first signal is inputted to the signal outputting unit.
Further in this case, the predetermined delay amount can be variably adjusted.
In this case, the signal outputting unit inputs the first signal prior to the generation signal and outputs the first signal until inputting the generation signal after inputting the first signal and outputs the generation signal instead of the first signal when inputting the generation signal.
Also in this case, the signal outputting unit inputs the first signal prior to the generation signal and outputs the first signal until inputting the generation signal after inputting the first signal and outputs the generation signal instead of the first signal when inputting the generation signal.
Further in this case, the signal outputting unit inputs the first signal prior to the generation signal and outputs the first signal until inputting the generation signal after inputting the first signal and outputs the generation signal instead of the first signal when inputting the generation signal.
In this case, the signal outputting unit inputs the first signal prior to the generation signal and outputs the first signal until inputting the generation signal after inputting the first signal and outputs the generation signal instead of the first signal when inputting the generation signal.
In order to achieve still another aspect of the present invention, a semiconductor apparatus, includes: a latch circuit latching a first signal to output the first signal as a second signal in response to a clock signal; a control signal generating unit generating a control signal based on the first signal and the second signal; and a signal outputting unit inputting the first and second signals to output one of the first and second signals in response to the control signal.
In order to achieve yet still another aspect of the present invention, a semiconductor apparatus, includes: a latch circuit latching a first signal to output the first signal as a second signal in response to a clock signal; a control signal generating unit generating a control signal based on the first signal and the clock signal; and a signal outputting unit inputting the first and second signals to output one of the first and second signals in response to the control signal.
In order to achieve still another aspect of the present invention, a semiconductor memory apparatus provided on a chip, includes: a memory cell array including a plurality of memory cells; and a selecting signal generating unit generating a selecting signal to select one of the plurality of memory cells, and wherein the selecting signal generating unit includes: a delay unit inputting a first signal from a first position of the chip to output a first delay signal obtained by delaying the first signal by a predetermined delay amount; a control signal generating unit inputting the first signal and the first delay signal to generate a control signal based on the first signal and the first delay signal; and a signal outputting unit inputting the first signal and a generation signal to output one of the first signal and the generation signal as the selecting signal in response to the control signal, wherein the generation signal is generated based on the first signal and a second signal, the second signal being inputted from a second position of the chip.
In this case, the predetermined delay amount is a substantially identical with a time that elapsed before the generation signal is inputted to the signal outputting unit after the first signal is inputted to the signal outputting unit.
Also in this case, the predetermined delay amount is longer than a time that elapsed before the generation signal is inputted to the signal outputting unit after the first signal is inputted to the signal outputting unit.
Further in this case, the predetermined delay amount can be variably adjusted.
In this case, the predetermined delay amount corresponds to a signal transmission delay resulted from a wiring provided between the first and second positions.
Also in this case, a logic operation is performed on the first and second signals to generate the generation signal, and wherein the predetermined delay amount corresponds to a logic delay when the logic operation is performed.
Further in this case, the delay unit is constituted by a long wiring.
In this case, the delay unit is constituted by a long wiring provided between the first and second positions.